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| S524AD0XD1/D0XF1 128K/256K-bit Serial EEPROM for Low Power Data Sheet OVERVIEW The S524AD0XD1/D0XF1 serial EEPROM has a 128K/256K-bit (16,384/32,768 bytes) capacity, supporting the standard I2CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 64 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524AD0XD1/D0XF1 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface * * Two-wire serial interface Automatic word address increment * Operating Characteristics * Operating voltage -- 1.8 V to 5.5 V Operating current -- Maximum write current: < 3 mA at 5.5 V -- Maximum read current: < 400 A at 5.5 V -- Maximum stand-by current: < 1 A at 5.5 V * Operating temperature range -- - 25C to + 70C (commercial) -- - 40C to + 85C (industrial) * Operating clock frequencies -- 400 kHz at standard mode -- 1 MHz at fast mode * Electrostatic discharge (ESD) -- 5,000 V (HBM) -- 500 V (MM) Packages * 8-pin DIP, and TSSOP EEPROM * * * * * * * 128K/256K-bit (16,384/32,768 bytes) storage area 64-byte page buffer Typical 3 ms write cycle time with auto-erase function Hardware-based write protection for the entire EEPROM (using the WP pin) EEPROM programming voltage generated on chip 500,000 erase/write cycles 50 years data retention 8-1 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET SDA Start/Stop Logic HV Generation Timing Control WP Control Logic SCL Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 16,384 x 8 bits 32,768 x 8 bits A0 A1 A2 Column Decoder Data Register DOUT and ACK Figure 8-1. S524AD0XD1/D0XF1 Block Diagram 8-2 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM VCC WP SCL SDA S524AD0XD1/D0XF1 A0 A1 A2 VSS NOTE: The S524AD0XD1/D0XF1 is available in 8-pin DIP, and TSSOP package. Figure 8-2. Pin Assignment Diagram Table 8-1. S524AD0XD1/D0XF1 Pin Descriptions Name A0, A1, A2 Type Input Description Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or VSS of the device. These pins are internally pulled down to VSS. Ground pin. Bi-directional data pin for the I2C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VDD. Schmitt trigger input pin for serial clock input. Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. Single power supply. Circuit Type 1 VSS SDA - I/O - 3 SCL WP Input Input 2 1 VCC - - NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. 8-3 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET A0, A1, A2, WP SCL Noise Filter Figure 8-3. Pin Circuit Type 1 Figure 8-4. Pin Circuit Type 2 SDA Data Out VSS Noise Filter Data In Figure 8-5. Pin Circuit Type 3 8-4 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM FUNCTION DESCRIPTION I2C-BUS INTERFACE The S524AD0XD1/D0XF1 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as a "transmitter" and any device that gets data from the bus is a "receiver." The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524AD0XD1/D0XF1 devices can be connected to the same I2C-bus as slaves (see Figure 8-6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active. VCC VCC R R SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) MCU To VCC or VSS To VCC or VSS To VCC or VSS To VCC or VSS S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 Slave 2 S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 Slave 3 S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 Slave 8 S524AD0XD1/ D0XF1 Tx/Rx A0 A1 A2 Figure 8-6. Typical Configuration 8-5 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET I2C-BUS PROTOCOLS Here are several rules for I2C-bus transfers: -- A new data transfer can be initiated only when the bus is currently not busy. -- MSB is always transferred first in transmitting data. -- During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I2C-bus interface supports the following communication protocols: * * * Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active. Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in High level. All bus commands must be preceded by a start condition. Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in High level. All bus operations must be completed by a stop condition (see Figure 8-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 8-7. Data Transmission Sequence * Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits of data (see Figure 8-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected but no stop condition, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. * 8-6 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 8-8. Acknowledge Response from Receiver * Slave Address: After the master initiates a start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the "device identifier." The identifier for the S524AD0XD1/D0XF1 is "1010B". The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1, and A2 pins. Using this addressing scheme, you can cascade up to eight S524AD0XD1/D0XF1s on the bus (see Figure 8-9 below). Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is "1", a read operation is executed. If it is "0", a write operation is executed. * Device Identifier Slave Address 1 0 1 0 Device Select A2 A1 A0 R/W First (High) Address First Word Address X(2) A14(1) A13 A12 A11 A10 A9 A8 Second (Low) Address Second Word Address A7 A6 A5 A4 A3 A2 A1 A0 NOTES: 1. The A14 is "don't care" for the S524AD0XD1. 2. X = Don't care Figure 8-9. Device Address 8-7 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET BYTE WRITE OPERATION A write operation requires 2-byte word addresses, the first (high) word address and the second (low) word address. In a byte write operation, the master transmits the slave address, the first word address, the second word address, and one data byte to the S524AD0XD1/D0XF1 slave device (see Figure 8-10). Start Slave Address First Word Address Second Word Address Data Stop A C K A C K A C K A C K Figure 8-10. Byte Write Operation Following a start condition, the master puts the device identifier (4 bits), the device address (3 bits), and an R/W bit set to "0" onto the bus. Upon the receipt of the slave address, the S524AD0XD1/D0XF1 responds with an ACK. And the master transmits the first word address, the second word address, and one byte data to be written into the addressed memory location. The master terminates the transfer by generating a stop condition, at which time the S524AD0XD1/D0XF1 begins the internal write cycle. While the internal write cycle is in progress, all S524AD0XD1/D0XF1 inputs are disabled and the S524AD0XD1/D0XF1 does not respond to any additional request from the master. 8-8 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM PAGE WRITE OPERATION The S524AD0XD1/D0XF1 can also perform 64-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 63 additional bytes. The S524AD0XD1/D0XF1 responds with an ACK each time it receives a complete byte of data (see Figure 8-11). Start Slave Address First Word Address Second Word Address Data Byte 0 Data Byte N (N 63) Stop A C K A C K A C K A C K A C K A C K Figure 8-11. Page Write Operation The S524AD0XD1/D0XF1 automatically increments the word address pointer each time it receives a complete data byte. When one byte is received, the internal word address pointer increments to the next address so that the next data byte can be received. If the master transmits more than 64 bytes before it generates a stop condition to end the page write operation, the S524AD0XD1/D0XF1 word address pointer value "rolls over" and the previously received data is overwritten. If the master transmits less than 64 bytes and generates a stop condition, the S524AD0XD1/D0XF1 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there would be no response to additional requests from the master until the internal write cycle is completed. 8-9 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the S524AD0XD1/D0XF1 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device to determine whether the write cycle is completed. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the S524AD0XD1/D0XF1 remains busy with the write operation, no ACK is returned. When the S524AD0XD1/D0XF1 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 8-12). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/W bit = "0" No ACK = "0" ? Yes Start Next Operation Figure 8-12. Master Polling for an ACK Signal from a Slave Device 8-10 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the S524AD0XD1/D0XF1. This write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to it is ignored. The S524AD0XD1/D0XF1 will acknowledge slave address, word address, and data bytes. But the write cycle will not be started when a stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to protect data from being overwritten. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address "n", the next read operation would be to access data at address "n+1". When the S524AD0XD1/D0XF1 receives a slave address with the R/W bit set to "1", it issues an ACK and sends the eight bits of data. In a current address byte read operation, the master does not acknowledge the data, and it generates a stop condition, forcing the S524AD0XD1/D0XF1 to stop the transmission (see Figure 8-13). Start Slave Address Data Stop A C K N O A C K Figure 8-13. Current Address Byte Read Operation 8-11 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. This operation is performed in the following steps: 1. The master first issues a start condition, the slave address, and the word address (the first and the second addresses) to be read. (This step sets the internal word address pointer of the S524AD0XD1/D0XF1 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to "1". 3. The S524AD0XD1/D0XF1 then sends an ACK and the 8-bit data stored at the pointed address. 4. At this point, the master does not acknowledge the transmission, generating a stop condition. 5. The S524AD0XD1/D0XF1 stops transmitting data and reverts to stand-by mode (see Figure 8-14). Start Slave Address First Word Address Second Word Address Start Slave Address Data Stop A C K A C K A C K A C K N O A C K Figure 8-14. Random Address Byte Read Operation 8-12 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: current address sequential read operation, and random address sequential read operation. The first data is sent in either of the two ways, current address byte read operation or random address byte read operation described earlier. If the master responds with an ACK, the S524AD0XD1/D0XF1 continues transmitting data. If the master does not issue an ACK, generating a stop condition, the slave stops transmission, ending the sequential read operation. Using this method, data is output sequentially from address "n" followed by address "n+1". The word address pointer for read operations increments to all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer "rolls over" and the S524AD0XD1/D0XF1 continues to transmit data for each ACK it receives from the master (see Figure 8-15). Start Slave Address Data (n) Data (n + x) ~ ~ A C K A C K A C K N O A C K Figure 8-15. Sequential Read Operation 8-13 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET ELECTRICAL DATA Table 8-2. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature Electrostatic discharge Symbol VCC VIN VO TA TSTG VESD Conditions - - - - - HBM MM Rating - 0.3 to + 7.0 - 0.3 to + 7.0 - 0.3 to + 7.0 - 40 to + 85 - 65 to + 150 5000 500 Unit V V V C C V Table 8-3. D.C. Electrical Characteristics (TA = - 25 C to + 70 C (Commercial), - 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Input low voltage Input high voltage Input leakage current Output leakage current Output Low voltage Symbol VIL VIH ILI ILO VOL VIN = 0 to VCC VO = 0 to VCC IOL = 0.15 mA, VCC = 1.8 V IOL = 2.1 mA, VCC = 2.5 V Supply current Write ICC1 ICC2 Read ICC3 ICC4 Stand-by current ICC5 ICC6 VCC = 5.5 V, 400 kHz VCC = 1.8 V, 100 kHz VCC = 5.5 V, 400 kHz VCC = 1.8 V, 100 kHz VCC = SDA = SCL = 5.5 V, all other inputs = 0 V VCC = SDA = SCL = 1.8 V, all other inputs = 0 V - - - - - - - - - - - - Conditions SCL, SDA, A0, A1, A2 Min - 0.7 VCC - - - Typ - - - - - Max 0.3 VCC - 10 10 0.2 0.4 3 1 0.4 60 1 1 A A mA Unit V V A A V 8-14 DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM Table 8-3. D.C. Electrical Characteristics (Continued) (TA = - 25 C to + 70 C (Commercial), - 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Input capacitance Symbol CIN Conditions 25 C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin 25 C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin Min - Typ - Max 10 Unit pF Input/Output capacitance CI/O - - 10 Table 8-4. A.C. Electrical Characteristics (TA = - 25 C to + 70 C (Commercial), - 40 C to + 85 C (Industrial), VCC = 1.8 V to 5.5 V) Parameter Symbol Conditions VCC = 1.8 to 5.5 V (Standard Mode) Min External clock frequency Clock High time Clock Low time Rising time Falling time Start condition hold time Start condition setup time Data input hold time Data input setup time WP hold time WP setup time Stop condition setup time Bus free time Data output valid from clock low Noise spike width Write cycle time Fclk tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tHD:WP tSU:WP tSU:STO tBUF tAA tSP tWR - - - SDA, SCL SDA, SCL - - - - - - - Before new transmission - - - 0 0.6 1.3 - - 0.6 0.6 0 0.1 1.3 0.6 0.6 1.3 0.1 - - Max 400 - - 0.3 0.3 - - - - - - - - 0.9 50 5 VCC = 2.5 to 5.5 V (Fast Mode) Min 0 0.5 0.5 - - 0.25 0.25 0 0.1 1.3 0.6 0.25 0.5 0.05 - - Max 1000 - - 0.3 0.1 - - - - - - - - 0.55 50 5 kHz s s s s s s s s s s s s s ns ms Unit 8-15 S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET tF SCL tSU:STA SDA In tLOW tHIGH tR tHD:STA tHD:DAT tSU:DAT tSU:STO tAA SDA Out (Protected) WP (Unprotected) tSU:WP tBUF tHD:WP Figure 8-16. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ SDA WORDn 8th Bit ACK tWR Stop Condition Start Condition Figure 8-17. Write Cycle Timing Diagram ~ ~ 8-16 |
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